AR# 11774: LogiCORE Viterbi Decoder v1.0 - 4.1i CORE Generator In a Viterbi Decoder core behavioral simulation, the "rdy" signal goes high one clock early
LogiCORE Viterbi Decoder v1.0 - 4.1i CORE Generator In a Viterbi Decoder core behavioral simulation, the "rdy" signal goes high one clock early
Keywords: FEC, forward error correction, Viterbi
General Description: In a parallel Viterbi decoder, when c_has_nd = 0 and c_has_rdy=1, the rdy signal goes high one clock too early in the behavioral model.
The signal subsequently remains high in both the structural and behavioral code.
This is a behavioral model problem only, and the core implementation will work properly. Our developers are aware of the simulation mismatch and are working on a fix.
If you cannot work around this, you can perform a gate-level simulation of the core using the EDIF netlist; do this by taking the EDIF netlist for the core through NGDBuild, then running NGD2VHDL. For more information on this process, please refer to (Xilinx Solution 8065).