UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 11776

HDL Bencher - ModelSimXE reports "ERROR: file_tb.vhd(line#): Prefix of index must be an array" when compiling for simulation

描述

Keywords: HDL Bencher, Prefix, array, ModelSimXE, index, read, write

Urgency: Standard.

General Description:
When I run an HDL Bencher-generated testbench in ModelSimXE, the following error (or multiple instances of it) is reported:

"ERROR: file_tb.vhd(line#): Prefix of index must be an array".

The syntax of the HDL seems to be correct; however, in the line number mentioned in the error, there may be references to reserved "signals" that are used by HDL Bencher.

解决方案

As Ports and Signals cannot have the same names in VHDL; if this is the case, change the Port names of the modules you wrote. (Check for this in the testbench.)

Additionally, check for reserved words such as "Read" or "Write".
AR# 11776
日期 12/11/2006
状态 Archive
Type 综合文章
的页面