AR# 11827


4.1i CORE Generator - How do I create a distributed RAM FIFO that is deeper than 255?


Keywords: COREGen, FIFO, distributed, RAM, depth, 255, IP, update, v3, v4

Urgency: Standard

General Description:
CORE Generator will not allow me to create distributed RAM-based FIFOs with depths that are greater than 255. How do I create deeper distributed FIFOs?


For information about synthesizing your own synchronous/asynchronous FIFOs, please refer to the following Xilinx Application notes:

- "170 MHz FIFOs using the Virtex Block SelectRam+ Feature" (
- "Data-Width Conversion FIFOs Using the Virtex Block SelectRAM Memory" (

The following links lead to the accompanying source files:
AR# 11827
日期 09/11/2003
状态 Archive
Type 综合文章
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