AR# 11845


Async_FIFO_v3_0 - Compilation order problems


When compiling XilinxCoreLib simulation models or attempting to simulate my design with the CORE Generator Asynchronous FIFO, I receive the following message from my simulator:

"Recompile /products//vhdl/mti/5.4e/sol/XilinxCoreLib.async_fifo_v3_0 because /products/vhdl/mti/5.4e/sol/XilinxCoreLib.async_fifo_comps has changed."


This problem will be fixed in the 4.1i release of the Xilinx Implementation tool.

A possible work-around is to search in the file "async_fifo_v3_0.vhd," and replace every instance of "async_fifo_pkg" with "async_fifo_v3_pkg". Then, recompile XilinxCoreLib.
AR# 11845
日期 07/28/2010
状态 Archive
Type 综合文章
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