How do I determine the transition times of FPGA outputs? Does Xilinx specify these parameters?
Given the speed at which today's advanced semiconductors switch, PCB traces as small as one inch appear as transmission lines. Signal behavior can thus be influenced by transmission line effects such as crosstalk and ringing.
Signal behavior is also affected by variations in process, temperature, and power supply. Because of these dependencies, Xilinx is unable to specify output transition times in a general manner. The best way to determine how a switching output will behave is to perform an IBIS simulation.
IBIS models for Xilinx devices can be found at:
For more information regarding Signal Integrity Engineering, visit "SI Central":