For UltraScale, 7 Series, Zynq-7000, Virtex-II/-II Pro/-4/-5/-6, Spartan-3 /3E /3A /3AN /3A DSP /6: for differential (such as LVDS) and voltage-referenced (such as SSTL/HSTL) inputs,
1) Is a VCCO supply still required to be at a specific level for input (or bi-directional) I/O pins?
2) Is a VCCO supply required in an unused bank?
1) For differential inputs such as LVDS, and voltage-referenced (VREF) based inputs such as SSTL, HSTL, and HSUL, the inputs/receiver circuits are either powered by VCCAUX, or by VCCAUX_IO if it exists (such as with 7 Series and UltraScale HP banks). Therefore, the differential and VREF I/O standards, are considered "non-VCCO-dependent", and the VCCO level does not necessarily need to be kept at the same voltage level required for those I/O standard outputs. However, there are some important caveats:
a) Data Sheet requirements for VIN (voltage range at the SelectIO pins) will always need to be met. This includes both Absolute Maximum Ratings for VIN (typically in Table 1), as well as Recommended Operating Conditions for VIN (typically in Table 2).
b) Input power-clamp diodes can become forward-biased if the VIN exceeds VCCO by the diode threshold voltage (~0.5V). This can happen if VCCO is un-powered or set at a lower voltage level. To avoid this, VCCO voltage level should be greater than the expected input high voltage (plus any overshoot), less the 0.5V diode voltage. For example, if the maximum input high voltage is 2.5V (including overshoot), VCCO should be greater than 2.5V - 0.5V = 2.0V.
NOTE: The power-clamp diodes that exist in most Xilinx devices including 7 Series, Zynq-7000, UltraScale, Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5, Virtex-6, Spartan-3 and Spartan-3E devices are not I/O standard-dependent -- they are always present. However, some families such as Virtex, Spartan-3A, and Spartan-6 have an optional floating N-well that is only biased if a PCI I/O standard is configured in the I/O. For those limited families, the power-clamp diode is only present in the I/O if one of the PCI I/O standards is configured for the particular I/O pin.
c) A VCCO supply is always required to achieve proper termination on DCI split-termination inputs for those families and bank-types that support DCI, and/or for use of the optional internal differential termination resistor (DIFF_TERM = TRUE). For more information, see the corresponding FPGA SelectIO User Guides "Digital Controlled Impedance", and differential termination resistor sections.
2) In the case of a completely unused I/O bank, leaving the VCCO pins of unused I/O banks floating reduces the level of ESD protection on these pins and the I/O pins in the bank and is generally not recommended. However, ESD events at the unconnected solder balls in the inner rows of the pin array are unlikely and not considered a high risk.