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AR# 12051

HDL Bencher - Verilog ports that have the same name, but are written out different cases, produce errors when loaded in HDL Bencher.


Keywords: case, sensitive, port, Verilog

Urgency: Standard

General Description:
If a Verilog module has a port named "DATA" and another port named "data", they will be seen as the same port by HDL Bencher. This causes errors.


In order to avoid this naming conflict, simply rename one of the modules
AR# 12051
日期 12/11/2006
状态 Archive
Type 综合文章