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AR# 12076

XST - XST issues errors for modules that are declared multiple times

描述

General Description: 

XST issues an error for modules that are declared multiple times. This error occurs in designs that have an instantiated Unified Library primitive and a module declaration for the component in the Verilog source file.

解决方案

To solve this issue, remove the module declarations from the Verilog source code since the components are already declared in the system libraries (these libraries are also read by XST during synthesis).

AR# 12076
日期 05/14/2014
状态 Archive
Type 综合文章
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