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AR# 12087

4.1i Project Navigator - The ABEL-Verilog flow fails during simulation if the module is not written in lower-case letters


Keywords: ABEL, Verilog, post-fit, simulation

Urgency: Standard

General Description:
The Verilog test fixture generated from test vectors in the ABEL source design incorrectly refers to the design module using all lower-case letters; this will not match the actual design module if any upper-case letters have been used there, and the ABEL-Verilog flow fails during simulation.


To avoid this problem, either switch to the ABEL-VHDL flow (which is not case-sensitive), or change your design module name so that it contains all lower-case letters.

NOTE: This does not affect Verilog test fixtures written by the user.
AR# 12087
日期 08/11/2003
状态 Archive
Type 综合文章