UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 12176

4.1i Project Navigator - Several properties cause errors on pins that use ABEL bus notation

描述

Keywords: ABEL, properties, bus, translate, error

Urgency: Standard

General Description:
Xilinx properties of the form "name=value" (such as INIT, IOSTANDARD and PWR_MODE) cause errors during the Translate process when they are applied to ABEL pins that are defined using bus notation (e.g., "BUS [3..0] q PIN;").

解决方案

If these errors occur, specify the affected properties in a UCF instead of the source design.

NOTE: This does not affect pins that are defined using set notation (e.g, "[q3..q0] PIN;"), internal nodes, or properties that have no value field (e.g., "FAST").

This problem is fixed in the latest 4.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.1i Service Pack 2.
AR# 12176
日期 08/11/2003
状态 Archive
Type 综合文章
的页面