AR# 12288: 4.1i ISE - How do the synthesis tools push registers/flip-flops into the IOB for the Virtex family?
4.1i ISE - How do the synthesis tools push registers/flip-flops into the IOB for the Virtex family?
To push registers/flip-flops into the IOBs using synthesis, directives use the Process Properties for the synthesis tool in ISE.
In order for the FFs to be placed in the IOBs, these rules must be followed:
1. All FFs to be pulled into the IOB must have a fanout of 1. This applies to output and 3-state enable registers. For example, if a 32-bit bidirectional bus exists, then the 3-state enable signal must be replicated in the original design so that it will have a fanout of 1.
2. All FFs must share the same clock and reset signal (although they can have independent clock enables).
- Under "Synthesize Process Properties", choose the Xilinx Specific Options tab.
- Set the value of "Pack I/O registers into IOBs" to "Yes".
- Run "Edit Constraints" under Synthesize => Create Functional Structure.
- Under the Ports tab, set the value of "Use I/O Reg" to "True" for each port with a register that needs to be pushed into the IOB.
- Under "Synthesize", run "Edit Constraint File". This will bring up the constraints editor.
- Under the Attributes tab, choose your port and select the "syn_useioff" attribute for it.
- Under "Synthesize Process Properties", choose the Architecture Options tab.