UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 12399

4.1i CPLD XPLA3 Tsim - Negative edge-triggered product term clocks fail timing simulation

描述

Keywords: 4.1i, 4.2i, CoolRunner-II, CPLD, negative, edge, clock, simulation

Urgency: Standard

General Description:
Negative edge-triggered product term clocks fail timing simulation. (They simulate as if they were positive edge-triggered.)

解决方案

This issue appears only for product term clocks (rather than global or universal clocks).

This problem is fixed in the latest 4.2i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.2i Service Pack 2.
AR# 12399
日期 08/05/2003
状态 Archive
Type 综合文章
的页面