AR# 12406: Virtex-II/-II Pro - How do I ensure a 50/50 duty cycle for my clock-forwarding application?
Virtex-II/-II Pro - How do I ensure a 50/50 duty cycle for my clock-forwarding application?
My clock input has a 50/50 duty cycle. However, when I forward this clock to an output, I do not see a 50/50 duty cycle. How do I output or forward a 50/50 duty cycle clock?
The following factors could affect your duty cycle:
1. You MUST make sure that the I/O Standard can switch fast enough to keep a 50/50 duty cycle. You must verify this by performing an IBIS simulation on the signal.
2. Some I/O Standards have asymmetric rise and fall times that can contribute to duty cycle distortion at a higher frequency. This can be seen in the IBIS simulation as well. The DCI versions of HSTL, SSTL, and LVCMOS will have better symmetry.
3. To guarantee a 50/50 duty cycle above 100 MHz, you MUST use a DCM in duty cycle correction mode.
4. For designs above 250 MHz, use both CLK0 and CLK180 of the DCM as follows:
- Connect the CLK0 of the DCM to a BUFG to the C0 of a DDR FF; connect the D0 input to VCC. - Connect the CLK180 of the DCM to another BUFG to the C1 of the DDR FF, with the D1 input connected to GND.
- For the suggested configuration of DDR FF above, do not use the local clock inversion on the DDR FF. - You may see ~140 ps subtracted from the clock high time if you use the local clock inversion in the IOB or CLB. This is the worst-case number, and it is internal. Hence, for designs below 250 MHz, using the local CLB/IOB inversion will still give 45 - 55% internally. - Configuring the DDR, as described above, allows the clock signal to stay on the clock tree, and best represents what the design is seeing.
5. If more than one DCM output is used, you must connect to a BUFGMUX on the same side of the chip. Furthermore, each DCM can connect to a maximum of four BUFGMUXs and must be of a certain combination. For more information, refer to (Xilinx Answer 12246) /> 6. At a frequency greater than 250 MHz, consider using the LVDS I/O Standard.