AR# 12422


LogiCORE SPI-4.2 (POS-PHY L4) v3.x - VHDL simulation for PL4 does not work with default parameters


General Description:

VHDL simulation for PL4 does not work with default parameters.


To use the VHDL Demo testbench, you must first apply the following corrections and patch:

Step 1:

When the gate-level (post-NGDBuild) PL4 VHDL simulation file is generated using NGD2VHDL, you must use the "xon -FALSE" option, as in the following example:

ngd2vhdl -xon false -w PL4_Top.ngd pl4.vhd

(NOTE: Steps 2 and 3 are not needed if you are using version 4.1i or higher of the Xilinx software tools. You must make these changes if you are using Xilinx 3.1i software.)

Step 2:

Edit the VHDL simulation file that is generated by the NGD2VHDL file.

In the instantiation of the instance PL4_CORE_PL4_CLK_RSCLK_DCM, change the line from:




Step 3:

Change the delay of the primitive X_INV in the simprim_VITAL.vhd and simprim_Vcomponents.vhd files.

The simprim_VITAL.vhd and simprim_Vcomponents.vhd files are available at ($XILINX is the directory in which the local copy of the Xilinx tools is installed):


In the entity declaration of X_INV, change the line from:

tpd_I_O : VitalDelayType01 := (0.100 ns, 0.100 ns);


tpd_I_O : VitalDelayType01 := (0.000 ns, 0.000 ns);

Recompile the simprim_Vpackage.vhd, simprim_VITAL.vhd, and simprim_Vcomponents.vhd files.

Step 4:

Compile the patch for the DCM model. The patched file is included in the PL4 zip file at:


NOTE: You must replace the "X" in the following file names with the configuration that is in use:



Step 5:

Compile the following files:




Finally, load the macro "" to run the gate-level VHDL simulation file.

AR# 12422
日期 05/03/2010
状态 Archive
Type 综合文章
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