We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 12516

4.1i CPLD XPLA3 Hprep6 - The JEDEC produced from the Xilinx software does not disable the ISP pins (JTAG)


Keywords: 4.1i, XPLA3, ISP, JEDEC

Urgency: Hot

General Description:
The JEDEC produced from the 4.1i Xilinx software does not disable the ISP pins, leaving them dedicated to JTAG functionality; this occurs regardless of the setting in the ISE GUI. The report file does show that the setting for "Reserve JTAG Port Pins" was read in properly.


This is fixed in the latest 4.1i Service Pack, available at:
The first version of software to contain this fix is 4.1i Service Pack 2.
AR# 12516
日期 08/05/2003
状态 Archive
Type 综合文章