AR# 12546


4.1i XST - "ERROR:Xst:850 - "project_file.v", line xx: Unsupported While Statement"


Keywords: While, loop, Verilog, XST, for, VHDL

Urgency: Standard

General Description:
When I use a "while" loop in Verilog, the following error is reported:

"ERROR:Xst:850 - "project_file.v", line xx: Unsupported While Statement."


Currently, "while" loops are not supported in Verilog. They will be supported in a future XST release.

Certain "while" loop constructs are supported for VHDL. This was first implemented in version 4.1i, Service Pack 3.
This service pack is available at:
AR# 12546
日期 08/06/2003
状态 Archive
Type 综合文章
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