The I/Os I configure with DCI do not work as expected. How do I debug this?
To debug your setup, try the following suggestions:
Software:
- Use the most recent software version and service pack. The latest software update is available at:
http://www.xilinx.com/support/download/index.htm
Select the Updates and Service Packs tab.
VRN and VRP:
- Ensure that resistors are connected and are placed on the correct bank.
- VRN should be connected to VCCO (not VCC or VCCAUX).
- VRP should be connected to GND.
- On ES silicon, ALT_VRN/ALT_VRP pins (Banks 4 and 5) should not be used (refer to (Xilinx Answer 11208) for more information about using ALT_VRN/ALT_VRP vs. VRN/VRP).
- Compare a scope shot of your VRN/VRP waveforms to the example waveforms below (this will not be present if the bank is using only these outputs: HSTL_I_DCI, HSTL_3_DCI, SSTL2_I_DCI, SSTL3_I_DCI). Ensure that your waveforms have a similar shape. The absolute voltage levels and time scale are not important.
NOTE: VRP is the top waveform, and VRN is the bottom waveform.
Configuration
- VRN and VRP must be connected during configuration.
- VCCO must be set correctly during configuration.
- Set the Match_cycle option in BitGen. The default value for this is "NoWait". If you use DCI, the value should be set to a specific startup cycle (0 - 6).
The Match_cycle option will stall the start-up sequence at the selected phase until the DCI match signals are asserted. If you would like to use a DONE pin as an indicator that DCI has found a match, set the value to a start-up cycle before the DONE_cycle setting (the DONE_cycle default is 4, hence this can be set to a cycle of 3 or earlier).
NOTE:
- In the ISE 5.1i design tools, the default setting for the Match_cycle option is "Auto". With this setting, Match_cycle will be automatically set to "NoWait" if DCI is not used in the design, or to "2" if DCI is used in the design.
- For information on BitGen options, please see:
http://www.xilinx.com/support/documentation/index.htm
1. Select the Design Tools tab.
2. Click on ISE Foundation/ISE WebPACK.
3. Select the latest release. A pdf containing all the software manual will open.
4. Select the Development System Reference Guide.
5. Select BitGen (Chapter 16 in ISE 10.1)
Next Steps:
If the above suggestions do not isolate the problem, please open a WebCase with Xilinx Customer Service at:
http://support.xilinx.com/support/clearexpress/websupport.htm
When you open your WebCase, please supply the following information:
1. The device and software version used.
2. The I/O standards used in the bank and whether they are used as input, output, or both.
3. A complete description of the issue(s).
AR# 12573 | |
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日期 | 12/15/2012 |
状态 | Active |
Type | 综合文章 |