General Description:
How do I obtain technical support for the Verplex/Xilinx formal verification flow?
Xilinx supports gate (post-PAR) to gate (post-PAR) verification using the Conformal LEC tool.
For any other verification (RTL to RTL, RTL to GATE, RTL to Post-Synthesis, Post-Synthesis to Gate), please contact Cadence to see if the desired verification flow is supported.
| AR# 12576 | |
|---|---|
| 日期 | 03/03/2014 |
| 状态 | Archive |
| Type | 综合文章 |