AR# 12638: 3.1i NGDBuild - "ERROR:Ngd:284 - NET 'clk_name' , which is the reference clock net for the OFFSET 'OFFSET = IN..."
AR# 12638
3.1i NGDBuild - "ERROR:Ngd:284 - NET 'clk_name' , which is the reference clock net for the OFFSET 'OFFSET = IN..."
描述
Keywords: 3.1, NGDBuild, reference, clock, pad
Urgency: Standard
General Description: When I use FPGA Express for synthesis, the following error occurs:
ERROR:Ngd:284 - NET 'clk_name' , which is the reference clock net for the OFFSET 'OFFSET = IN 20000.000000 pS BEFORE PCLK ;', is not a pad related net (not driven by a pad).
In 4K series chips (including Spartan and Spartan-XL), FPGA Express does not insert an IPAD component.
解决方案
1
To avoid this error, use the translate option "Create I/O Pads from Ports".
2
Also, if the clock signal is not going into a global clock pin, you may instantiate an IBUF component to drive the BUFG component.