AR# 12692


Signal and Power Integrity - What are "virtual" ground and power pins?


General Description:

What are "virtual" ground and power pins? How can they reduce power supply noise?


The following information applies to all Xilinx FPGAs and CPLDs.

A virtual ground or power pin is a user I/O that is programmed to drive Low or High, and is then externally tied to the PCB's ground or power plane, respectively. The virtual ground or power pin essentially provides an additional path for transient current to use, and consequently, decreases the power supply inductance and power supply noise (also referred to as ground bounce).

To maximize the effectiveness of a virtual ground or power pin, you should select an I/O standard (LVTTL24, PCI, or GTL) with high drive strength (low impedance). Generally, virtual grounds are preferable since they result in the most noise reduction. If you use both virtual ground and virtual power pins, they will be more effective if placed close together.

The utilization of virtual supply pins should NOT be used an excuse to disregard the SSO guidelines contained in the device data sheets. Virtual supply pins should be employed whenever possible as a supplemental measure against the effects of switching noise.

For a detailed discussion about managing SSO noise, please refer to (Xilinx XAPP689): "Managing Ground Bounce in Large FPGAs."

AR# 12692
日期 12/15/2012
状态 Active
Type 综合文章
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