AR# 12713

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Synopsys Formality/Verplex Conformal - Formal Verification fails while checking the post-PAR design

描述

General Description: 

Formal Verification fails while checking the post-PAR design.

解决方案

This problem can occur when the "-dp" option has been used in MAP. This option causes a pattern of "LUT driving a flip-flop" to get mapped into unused block RAMs. Since the formal verification tools cannot map the logic inside the block RAM to the RTL netlist, errors will be reported.  

 

To work around this problem, do not use the "-dp" option in MAP.

AR# 12713
日期 05/14/2014
状态 Archive
Type 综合文章
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