General Description: How do I code bidirectional LVDS buffers in VHDL and Verilog for a Virtex-II?
解决方案
1
The bidirectional LVDS solution in the Virtex-II architecture is identical to the Virtex-E solution. Since LVDS is intended for point-to-point applications, BLVDS (Bus-LVDS) is not an IEEE/EIA/TIA standard implementation and requires careful adaptation of I/O and PCB layout design rules.
VHDL, Verilog and UCF examples follow:
VHDL:
library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.vcomponents.all;
entity LVDS_IOBUFDS is port (CLK_p, CLK_n, DATA_p, DATA_n, Tin_p, Tin_n: in STD_LOGIC; IODATA_p, IODATA_n : inout STD_LOGIC; Q_p, Q_n : out STD_LOGIC); end LVDS_IOBUFDS;
architecture BEHAV of LVDS_IOBUFDS is
component IBUFDS is port (I : in STD_LOGIC; IB: in STD_LOGIC; O : out STD_LOGIC); end component;
component OBUFDS is port (I : in STD_LOGIC; O : out STD_LOGIC; OB : out STD_LOGIC); end component;
component IOBUFDS is port (I : in STD_LOGIC; T : in STD_LOGIC; O : out STD_LOGIC; IO: inout STD_LOGIC; IOB: inout STD_LOGIC); end component;
component IBUFGDS is port(I : in STD_LOGIC; IB: in STD_LOGIC; O : out STD_LOGIC); end component;
component BUFG is port(I : in STD_LOGIC; O : out STD_LOGIC); end component;
signal datain2 : std_logic; signal odata_out: std_logic; signal DATA_int : std_logic; signal Q_int : std_logic; signal CLK_int : std_logic; signal CLK_ibufgout : std_logic; signal Tin_int : std_logic;
attribute IOSTANDARD : string; attribute IOSTANDARD of UI1 : label is "BLVDS_25"; attribute IOSTANDARD of UI3 : label is "BLVDS_25"; attribute IOSTANDARD of UO1 : label is "BLVDS_25"; attribute IOSTANDARD of UIO2 : label is "BLVDS_25"; attribute IOSTANDARD of UIBUFG : label is "BLVDS_25";
begin UI1: IBUFDS port map (DATA_p, DATA_n, DATA_int); UI3: IBUFDS port map (Tin_p, Tin_n, Tin_int); UO1: OBUFDS port map (Q_int, Q_p, Q_n); UIO2: IOBUFDS port map (odata_out, Tin_int, datain2, IODATA_p, IODATA_n); UIBUFG : IBUFGDS port map (CLK_p, CLK_n, CLK_ibufgout); UBUFG : BUFG port map (CLK_ibufgout, CLK_int);
My_D_Reg: process (CLK_int, DATA_int) begin if (CLK_int'event and CLK_int='1') then Q_int <= DATA_int; end if; end process; -- End My_D_Reg