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  3. AR# 12761: 6.2 SYNPLIFY - How do I code bidirectional LVDS (BLVDS) buffers in VHDL and Verilog for a Virtex-II?

AR# 12761

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6.2 SYNPLIFY - How do I code bidirectional LVDS (BLVDS) buffers in VHDL and Verilog for a Virtex-II?

描述

Keywords: LVDS, BLVDS, code, buffers, VHDL, Verilog, Virtex-II

Urgency: Standard

General Description:
How do I code bidirectional LVDS buffers in VHDL and Verilog for a Virtex-II?

解决方案

1

The bidirectional LVDS solution in the Virtex-II architecture is identical to the Virtex-E solution. Since LVDS is intended for point-to-point applications, BLVDS (Bus-LVDS) is not an IEEE/EIA/TIA standard implementation and requires careful adaptation of I/O and PCB layout design rules.

VHDL, Verilog and UCF examples follow:

VHDL:

library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity LVDS_IOBUFDS is
port (CLK_p, CLK_n, DATA_p, DATA_n, Tin_p, Tin_n: in STD_LOGIC;
IODATA_p, IODATA_n : inout STD_LOGIC;
Q_p, Q_n : out STD_LOGIC);
end LVDS_IOBUFDS;


architecture BEHAV of LVDS_IOBUFDS is

component IBUFDS is
port (I : in STD_LOGIC;
IB: in STD_LOGIC;
O : out STD_LOGIC);
end component;

component OBUFDS is
port (I : in STD_LOGIC;
O : out STD_LOGIC;
OB : out STD_LOGIC);
end component;

component IOBUFDS is
port (I : in STD_LOGIC;
T : in STD_LOGIC;
O : out STD_LOGIC;
IO: inout STD_LOGIC;
IOB: inout STD_LOGIC);
end component;

component IBUFGDS is
port(I : in STD_LOGIC;
IB: in STD_LOGIC;
O : out STD_LOGIC);
end component;

component BUFG is
port(I : in STD_LOGIC;
O : out STD_LOGIC);
end component;

signal datain2 : std_logic;
signal odata_out: std_logic;
signal DATA_int : std_logic;
signal Q_int : std_logic;
signal CLK_int : std_logic;
signal CLK_ibufgout : std_logic;
signal Tin_int : std_logic;

attribute IOSTANDARD : string;
attribute IOSTANDARD of UI1 : label is "BLVDS_25";
attribute IOSTANDARD of UI3 : label is "BLVDS_25";
attribute IOSTANDARD of UO1 : label is "BLVDS_25";
attribute IOSTANDARD of UIO2 : label is "BLVDS_25";
attribute IOSTANDARD of UIBUFG : label is "BLVDS_25";

begin
UI1: IBUFDS port map (DATA_p, DATA_n, DATA_int);
UI3: IBUFDS port map (Tin_p, Tin_n, Tin_int);
UO1: OBUFDS port map (Q_int, Q_p, Q_n);
UIO2: IOBUFDS port map (odata_out, Tin_int, datain2, IODATA_p, IODATA_n);
UIBUFG : IBUFGDS port map (CLK_p, CLK_n, CLK_ibufgout);
UBUFG : BUFG port map (CLK_ibufgout, CLK_int);

My_D_Reg: process (CLK_int, DATA_int)
begin
if (CLK_int'event and CLK_int='1') then
Q_int <= DATA_int;
end if;
end process; -- End My_D_Reg

odata_out <= DATA_int and datain2;


end BEHAV;

2

Verilog:

module LVDS_IOBUFDS (CLK_p, CLK_n, DATA_p, DATA_n, Tin_p, Tin_n, IODATA_p, IODATA_n, Q_p, Q_n) ;

input CLK_p, CLK_n, DATA_p, DATA_n, Tin_p, Tin_n;
inout IODATA_p, IODATA_n;
output Q_p, Q_n;

wire datain2;
wire odata_in;
wire odata_out;
wire DATA_int;
reg Q_int;
wire CLK_int;
wire CLK_ibufgout;
wire Tin_int;

IBUFDS UI1 ( .I(DATA_p), .IB(DATA_n), .O( DATA_int)) /* synthesis xc_props = "IOSTANDARD=BLVDS_25" */;
IBUFDS UI2 (.I(Tin_p), .IB(Tin_n), .O (Tin_int)) /* synthesis xc_props = "IOSTANDARD=BLVDS_25" */;
OBUFDS UO1 ( .I(Q_int), .O(Q_p), .OB(Q_n)) /* synthesis xc_props = "IOSTANDARD=BLVDS_25" */;
IOBUFDS UO2 ( .I(odata_out), .O(datain2), .T(Tin_int), .IO(IODATA_p),.IOB(IODATA_n)) /* synthesis xc_props = "IOSTANDARD=BLVDS_25" */;
IBUFGDS UIBUFG ( .I(CLK_p), .IB(CLK_n), .O(CLK_ibufgout)) /* synthesis xc_props = "IOSTANDARD=BLVDS_25" */;
BUFG UBUFG (.I(CLK_ibufgout), .O(CLK_int));

always @ (posedge CLK_int)
begin
Q_int <= datain2;
end

assign odata_out = DATA_int;

endmodule

3

UCF:

If you wish to use the UCF method, delete the attribute statements from the VHDL or Verilog code, and add the following to a UCF:

INST UI1 IOSTANDARD=BLVDS_25;
INST UI2 IOSTANDARD=BLVDS_25;
INST UO1 IOSTANDARD=BLVDS_25;
INST UO2 IOSTANDARD=BLVDS_25;
INST UIBUFG IOSTANDARD=BLVDS_25;
AR# 12761
日期 04/20/2007
状态 Archive
Type 综合文章
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