AR# 12776


4.1i CPLD - ABEL XST-Verilog flow fails for a simulation with a mixed-case top module name


Keywords: 4.1i, CPLD, ABEL, XST, Verilog, simulation

Urgency: Standard

General Description:
I am using an ABEL-Verilog flow. When I invoke MXE for functional or timing simulation, it fails whenever the top module name contains any upper-case letters.

During the conversion from ABEL to Verilog, the module name is changed to lower-case characters; this creates a name mismatch, as Verilog is case-sensitive (unlike VHDL).


This problem is fixed in the latest 4.1i Service Pack, available at:
The first service pack containing the fix is 4.1i Service Pack 2.

If you do not wish to download the service pack, a work-around is to change the top-level module name so that it is written in lower-case characters.
AR# 12776
日期 08/05/2003
状态 Archive
Type 综合文章
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