General Description: Why does Xilinx support equivalency checking?
With device size and design complexity both increasing, functional simulation is becoming very time-consuming for both testbench generation and simulation run-time. Formal verification is attractive because of its short run-time and complete functional coverage.
In addition, formal verification is a proven technology in the ASIC design environment. As more ASIC designers begin to design with FPGAs, formal verification is becoming an increasingly important flow for design.
For related PrimeTime information, please also see the following Answer Records: