General Description: I have installed 4.1i IP Update #1; now, generating Dual or Single-Port Block Memory v4.0 and RAM-Based Shift Register v5.0 with a .coe file specified causes the following errors:
"ERROR: An internal error has occurred. To resolve this error, please consult the Answers Database at http://support.xilinx.com"
"ERROR: Sim has a problem implementing the selected core. Implementation netlist will not be generated."
"ERROR: SimGenerator: Failure of Sim to implement customization parameters core spblk_v4"
"ERROR: Did not generate EDIF implementation netlist (.EDN) file for core <spblk_v4>."
The core files will NOT be generated correctly.
The problem is that, when the .coe file is read in for core generation, the .mif file is written to one directory level above the project; therefore, the MIF file has the name "<project_dir><component_name>.mif".
For example: - A project directory called "test" exists; - You try to generate a core with component name "spblk_v4" with sched_ram .coe read in. - The file "testspblk_v4.mif" will be created one directory level above "test". - The core generation will fail.
Installation of the patch is the recommended fix; however, if you do not have access to the patch file right away, you can perform the following work-around:
- Copy "testspblk_v4.mif" to the project directory (one level down); - Rename the file to "spblk_v4.mif" (remove the project name); - Re-generate the core with the same parameters, and with the same COE files specified; - All the appropriate files should now be generated with the correct memory initialization in the EDIF netlist.