AR# 12918


Virtex-II/-II Pro, DCM - What is FINE_SHIFT_RANGE? How do I relate this specification to phase shift (DPS) operation?


In the Virtex-II/Pro DC and Switching Characteristics data sheet -> DCM Timing Parameters -> Miscellaneous Timing Parameters, a FINE_SHIFT_RANGE value is listed.  


What is FINE_SHIFT_RANGE? How do I relate this specification to phase shift (DPS) operation?  


This question relates to information in the Virtex-II/-II Pro User Guides at: 


Virtex-II Pro 

1. Go to:



The DCM can perform two kinds of phase shift: fixed mode and variable mode. 


More information on phase shift functionality of a Virtex-II/-II Pro DCM is available in: 

1. The Functional Description in the data sheet: Functional Description -> Detailed Description -> Digital Clock Manager (DCM); 

2. The User Guide: Design Considerations -> Digital Clock Manager (DCM). 


Two separate components limit the phase shift range: 


a: Range of the PHASE_SHIFT attribute 


This attribute is the numerator in the equation:  


phase shift (ns) = (PHASE_SHIFT/256) * PeriodCLKIN  


Its full range is always -255 to +255, both in FIXED and VARIABLE mode. However, its practical range varies with CLKIN frequency, as constrained by the next component:  


b: Range of the FINE_SHIFT_RANGE spec in the data sheet 


This value represents the total delay achievable by the phase shift delay line, which is a function of the number of delay taps used in the circuit. Across process, voltage, and temperature, this absolute range is guaranteed to be 10 ns.  


This range is different between FIXED and VARIABLE mode: 


Range (FIXED mode) = +/- FINE_SHIFT_RANGE = +/- 10 ns  

Range (VARIABLE mode) = +/- FINE_SHIFT_RANGE/2 = +/- 5 ns  


The reason for the difference is the following: In order for the VARIABLE mode to allow symmetric, dynamic sweeps from 255/256 to +255/256, the DCM sets the "zero phase skew" point as the middle of the 10 ns delay line; this divides the total delay line range in half. In FIXED mode, since the PHASE_SHIFT value never changes after configuration, the entire 10 ns delay line is available for insertion into either the CLKIN or CLKFB path to create either positive or negative skew.  


So, taking (a) and (b) together, the following conditions apply: 


- If CLKIN = 50 MHz (20 ns period), then (b) is limiting and the PHASE_SHIFT value is restricted to +/- 128 in FIXED mode and +/- 64 in VARIABLE mode. 


- If CLKIN = 100 MHz (10 ns period), then the FIXED mode PHASE_SHIFT value has its full range of +/- 255, while the VARIABLE mode is still limited by (2) to +/-128. 


- If CLKIN >= 200 MHz (5 ns period), then both FIXED and VARIABLE modes have the full PHASE_SHIFT range of +/- 255 available.  



- Xilinx only guarantees the FINE_SHIFT_RANGE as it is stated in the data sheet.  

- The STATUS(0) output will accurately reflect when a PHASE_SHIFT magnitude of 255 is exceeded, but it will not indicate when the guaranteed absolute range of the delay line is exceeded. For that constraint, the FINE_SHIFT_RANGE spec must be considered in the design.  

- Please see (Xilinx Answer 10972) for information on STATUS pins.

AR# 12918
日期 05/08/2014
状态 Archive
Type 综合文章
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