General Description: When I use the ChipScope Core Inserter, no ILA or ICON core appears in the design when I view it in FPGA Editor. Additionally, when I try to run the ChipScope Analyzer, the following error is reported:
"Core 0.0 is not valid or supported. Please verify that the instruction register lengths in the JTAG chain are properly specified."
When you create a new ChipScope project with Core Inserter and choose the location of the netlist, the program will select a default destination for the "output design netlist" and "output directory". However, the "output design netlist" is writing the NGO file to the wrong directory, so the implementation tools are not picking up a ChipScope core in the design.
To correct this, modify the default "output design netlist" path when you use Core Inserter to point to the netlist.
The path will be: <Project Directory>_ngo\project.ngo The path should be: <Project Directory>\_ngo\project.ngo
Adding the backslash character ("\") will allow the implementation tools to see the .ngo file that contains the ChipScope core information.