General Description: MAP optimizes registers with a constant input (VCC or GND). Therefore, when the RTL design is compared to the post-PAR design, Formality is unable to compare these points.
This file contains scripts that will parse the design netlist and create Synopsys Formality constraints, instructing Formality to correctly handle registers with constant inputs. The usage for the script is provided in the README provided in the patch zip file.
Synopsys also provides a work-around for this problem, which is documented in Solv-Net article "Formality-94.htm". This can be found on the SolvNet online database (http://solvnet.synopsys.com) by searching for the keywords "xilinx mapper".