描述

General Description:

The timing of RSCLK, relative to RStat[1:0], is not compliant with the SPI-4 Phase 2 specifications.

解决方案

This is not a design problem, but is a deliberate deviation from the specification to simplify board layout for users of the core.

Instead of transitioning the rising edge of RSCLK coincidentally with the changes of RStat[1:0] (as defined by Figure 6.15 of the OIF-SPI4-02.0 specification), RSCLK falls when RStat[1:0] changes and rises 1/2 a clock period later.

This produces ample sample and hold on RStat[1:0] relative to the rising edge of RSCLK. Without this deviation from the specification, the RSCLK signal would have to be delayed (relative to RStat[1:0]) or inverted on the PCB prior to driving OIF-compliant TSCLK or TStat[1:0] inputs.

By incorporating the clock inversion into the core's RSCLK output, you will avoid additional complexity at the PCB level. If this enhancement is not compatible with your requirements, Xilinx will deliver a fully compliant version on request. The timing at the TSCLK and TStat[1:0] inputs are compliant with the specification.

NOTE: In the PL4 v4.x of the core, you can turn this feature On or Off by using a static configuration signal located in a wrapper file. This static configuration signal is explained in the v4.x section of the PL4 data sheet.