UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13213

UniSim, SimPrim, Simulation - How do I simulate the DCM without connecting the CLK Feedback (CLKFB) port? (VHDL)

描述

How can I simulate the DCM without connecting the CLK Feedback (CLKFB) port?

解决方案

In order to simulate the DCM in VHDL without connecting the CLKFB port, the CLK_FEEDBACK generic must be passed to the simulation model as follows:

component DCM

-- synopsys translate_off

generic (

DFS_FREQUENCY_MODE : string := "LOW";

CLKFX_DIVIDE : integer := 1;

CLKFX_MULTIPLY : integer := 2 ;

CLK_FEEDBACK : string := "NONE"

);

-- synopsys translate_on

port ( CLKIN : in std_logic;

CLKFB : in std_logic;

DSSEN : in std_logic;

PSINCDEC : in std_logic;

PSEN : in std_logic;

PSCLK : in std_logic;

RST : in std_logic;

CLK0 : out std_logic;

CLK90 : out std_logic;

CLK180 : out std_logic;

CLK270 : out std_logic;

CLK2X : out std_logic;

CLK2X180 : out std_logic;

CLKDV : out std_logic;

CLKFX : out std_logic;

CLKFX180 : out std_logic;

LOCKED : out std_logic;

PSDONE : out std_logic;

STATUS : out std_logic_vector(7 downto 0)

);

end component;

Without this generic mapping, the simulation model will wait for the CLKFB port to go active, and will thus stay in its initial state.

A parameter does not need to be passed for a similar simulation in Verilog.

AR# 13213
日期 12/15/2012
状态 Active
Type 综合文章
的页面