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AR# 13224

4.1i ECS - A DRC check results in errors such as: "Library logical name UNISIM is not mapped to a host directory. (VSS-1071)"


Keywords: ISE, DRC, VSS-1071, VSS-573, VSS-124

Urgency: Standard

General Description:
For a schematic design, I perform a DRC check from the Design Entry Utilities in ISE 4.1. If I select FPGA Express as the synthesis tool, the following errors occur:

"Opening project d:\xilinx4\iseexamples\jc2_sch\__express_prj\jc2_top\jc2_top.exp
Removing the library unisim from design
Adding D:\Xilinx4\ISEexamples\jc2_sch\jc2_top.vhf to Express project
Analyzing D:\Xilinx4\ISEexamples\jc2_sch\jc2_top.vhf ...
Error: D:/Xilinx4/ISEexamples/jc2_sch/jc2_top.vhf line -4
Library logical name UNISIM is not mapped to a host directory. (VSS-1071) (FPGA-hci-hdlc-unknown)
Error: D:/Xilinx4/ISEexamples/jc2_sch/jc2_top.vhf line 7
No selected element named VCOMPONENTS is defined for this prefix. (VSS-573)
Error: D:/Xilinx4/ISEexamples/jc2_sch/jc2_top.vhf line 17
Previously analyzed design unit resides in library UNISIM, which has since become unmapped - check your setup files. (VSS-124) (FPGA-hci-hdlc-unknown)
Syntax Errors"


The schematic design will successfully complete synthesis and implementation despite these DRC errors.

Optionally, you may avoid the erroneous error messages by using XST for synthesis of ECS schematic designs.
AR# 13224
日期 01/08/2006
状态 Archive
Type 综合文章