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AR# 13286

4.1i XST - XST generates incorrect logic when a loop variable, signal, and/or port all have the same name

描述

Keywords: HDL, loop, variable, name, port

Urgency: Standard

General Description:
XST generates incorrect logic when a loop variable, signal, and/or port all have the same name. (XST does not properly keep track of all the names.)

解决方案

This problem is fixed in the latest 4.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.1i Service Pack 3.
AR# 13286
日期 08/06/2003
状态 Archive
Type 综合文章
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