UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13340

4.1i Virtex-II PAR - The placer is not taking clock analysis into account for Block RAMs

描述

Keywords: Block, RAM, BLKRAM, place, placer, placement

Urgency: Standard

General Description:
A problem with Block RAM placement has been discovered -- the placer is building internal macros that are not taking clock connectivity into account. The resulting macro has the potential for having no legal quadrant for placement.

解决方案

This problem is fixed in the latest 4.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates.
The first service pack containing the fix is 4.1i Service Pack 3.
AR# 13340
日期 10/23/2008
状态 Archive
Type 综合文章
的页面