AR# 13457: 3.x FPGA Express - How do I instantiate a black box component/module?
3.x FPGA Express - How do I instantiate a black box component/module?
How do I instantiate a black box component/module?
If there is a black box component/module named "black_box_core", a component/module declaration and a component/module instantiation must be made inside the proper VHDL/Verilog code, which will incorporate the black box into the design.
For example if ports a, b, and c exist ("a" and "b" being inputs and "c" being an output), you should have something similar to the following HDL:
component black_box_core is
port (a : in std_logic;
b : in std_logic;
c : out std_logic);
port map (a => sig1, b => sig2, c => sig3);
A module declaration consists of the module being declared with only the port listings and declarations. The module declaration can either be in a separate file or in the same file where the core is being instantiated.