AR# 13606


CPLD - Timing constraints cause my design to not fit


General Description:

A design fits with no timing constraints placed on it. However, when I add timing constraints, the design no longer fits in the device.


The software is attempting to speed up your critical paths by flattening the logic; as a result of the wider fan-ins into each function block, the design expands to the point where it can no longer fit.

Try the following solutions:

1. Use the "speed" option when fitting your design.

2. Ensure that you have no macrocells in the critical path in low-power mode. (This applies only to the XC9500/XL/XV families.)

3. Try targeting a faster speed grade device.

4. Relax the timing constraints.

AR# 13606
日期 12/15/2012
状态 Active
Type 综合文章
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