My design has an excessively large-magnitude Tdcmino, which is de-skewing my clock too much. What causes this? How do I fix it?
The Tdcmino number is the amount by which the DLL will de-skew the clock. A very negative Tdcmino (~10ns) can be caused by local routing being used in the feedback path. The DLL accounts for this long route, which overcompensates for the actual clock skew.
To investigate, check the feedback path in FPGA Editor; begin at the input pin, continue through the DCM and global buffer, and return back to the DCM. If any lines exist that cross the entire chip, a bad placement of the DCM and global buffers may be at fault, as this causes the router to use local routing for the feedback path. The extra delay in the feedback path will overcompensate for the clock path.
For more information on Tdcmino, please see (Xilinx Answer 13024).