AR# 13671

|

4.1i CORE Generator, Virtex-II, Asynchronous FIFO - Under what circumstances will the WR_ERR and the RD_ERR signals be activated?

描述

Keywords: Asynchronous FIFO, WR_ERR, RD_ERR

Urgency: Standard.

General Description:
For Asynchronous FIFO, under what circumstances will the WR_ERR and the RD_ERR signals be activated?

解决方案

The only time RD_ERR is active (goes high) is when the FIFO stack is empty and an attempt to read from the stack has been made.

The only time WR_ERR is active (goes high) is when the FIFO stack is full and an attempt to write to the stack has been made.
AR# 13671
日期 10/09/2003
状态 Archive
Type 综合文章
People Also Viewed