AR# 13701

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4.1i XST - "ERROR:Xst - file_name.v Line #. parse error"

描述

Keywords: parse, error, Verilog, endmodule, identifier

Urgency: Standard

General Description:
When synthesizing a 4.1i design, XST may return a "parse error" if it detects that the Verilog design is syntactically wrong.

This problem has been fixed with the release of software version 5.1i.

解决方案

1

This error may occur when a Verilog file does not have an "endmodule" to close the file. The tools parse through the source code, then move on to the unisim_comp.v file; however, as they do not see an "endmodule" keyword before they get to the unisim_comp.v file's "module" keyword, the tools will flag a syntax problem.

To resolve this error, look through the Verilog source files and add the keyword "endmodule" to any Verilog files that have an open "module" declaration.

2

When specifying constants, the Verilog specification allows you to omit the width of the constant, which allows the synthesis tool use a default constant width of 32 bits.

To work around this, specify the width of the declared constant.
AR# 13701
日期 08/06/2003
状态 Archive
Type 综合文章
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