AR# 1373: Foundation XVHDL: How to use I/O Flip-Flops
AR# 1373
Foundation XVHDL: How to use I/O Flip-Flops
Description
Keywords: IOB, infer, metamor, ifd, ofd
Versions: F6.x, F1.3/F1.4
Urgency: Standard
General Description:
How can I utilize the IOB flip-flops through Foundation XVHDL?
*Note: This solution applies only to the XVHDL (Metamor) compiler. If you are using the Express compiler, you may control the insertion of I/O Flip-flops through the Express Constraints GUI.
解决方案
1
Foundation 6.0.2 =================
The XVHDL compiler will infer an input or output flip-flop if all of the following criteria are met:
1. The design is compiled as a "chip". 2. The input or output to the flip-flop is also declared as a port in the top-level entity. If the input is declared as a port, it cannot be used as an input in any other process or signal assignment. 3. The flip-flop does not use the Preset or Clear pin, unless the Xilinx_GSR attribute is used with that preset/clr signal. See also (Xilinx Solution 1376). 4. For all families EXCEPT the XC4000E, the flip-flop does not use a clock enable.
In an XC4000E design, a flip-flop which meets criteria 1-3 and has a clock enable will infer an I/O flip-flop, since the XC4000E has this architectural feature.
--Example of I/O flip-flop inference --Note that since the flip-flops use a clock enable, only an --XC4000E design will infer I/O flip-flops in this case.
library IEEE; use IEEE.std_logic_1164.all;
entity IOB4KE is port (IN1, IN2, CLK, EN: in std_logic; OUT1: out std_logic); end IOB4KE;
architecture IOFF_CE of IOB4KE is signal A: std_logic; signal B: std_logic; begin process (CLK, EN) begin if CLK'event and CLK='1' then --CLK rising edge if EN='1' then -- clock enable A <= in1; end if; end if; end process;
process (CLK, EN) begin if CLK'event and CLK='1' then -- CLK rising edge if EN='1' then -- clock enable B <= in2; end if; end if; end process;
OUT1 <= A and B;
end IOFF_CE;
2
Instantiating I/O Flip-flops with Foundation 6.0.2 or Foundation F1.x XVHDL ======================================================
Below is an example of instantiating an Input Flip-flop (IFD) in a Foundation VHDL design. Note the use of the "Inhibit_buf" attribute which prevents the automatic insertion of an IBUF at the D input. This attribute would be used similarly on the Q output port of an OFD.
library IEEE; use IEEE.std_logic_1164.all;
entity in_flop is port ( d_in: in STD_LOGIC; clk_in: in STD_LOGIC; q_out: out STD_LOGIC ); attribute inhibit_buf: boolean; attribute inhibit_buf of d_in: signal is true; end in_flop;
architecture in_flop_arch of in_flop is
component IFD port (D: in STD_LOGIC; C: in STD_LOGIC; Q: out STD_LOGIC); end component;
begin
U1: IFD port map (d_in, clk_in, q_out);
end in_flop_arch;
3
Foundation F1.3/F1.4 ====================
With Foundation F1.3/F1.4, XVHDL infers only CLB flip-flops. In order for flip-flops which are able to be merged into IOBs to be used, the MAP program in the Implementation phase of the design flow must be used.
The default MAP setting is NOT to merge flip-flops into the IOBs. To enable this option in MAP, a customized template is required.
1. From the Design Manager, select Utilities -> Template Manager
2. Select the New button and give your custom template a name.
3. Select your template from the Template window and press the customize button.
4. In the Program Name selection box, enter: MAP. In the Program Options selection box, enter: -pr IOB.
5. Hit the OK button and exit the Template Manager by clicking the Close button.
6. When implementing the design, select your newly created template in the Implementation field of the Design Implementation Options window.