General Description: When I use a schematic macro containing CY4 primitives in an ECS-VHDL flow, the following error is reported:
"ERROR:OldMap:455 - The signal `GLOBAL_LOGIC0' on the CIN pin of CY4 symbol "XLXI/I1" (output signal=XLXI/C0) is a constant logic1 or logic0. Initially the signal was inappropriately driven by a logic1/0 constant comp. Use one of the FORCE-x modes to initiate a carry chain CIN signal."
Certain macros for the Spartan and XC4000 families contain carry logic primitives called "CY4"s. As the VHDL written by ECS includes FPGA "Don't Touch" attributes on these CY4 primitives, the CIN inputs become grounded if they are not utilized. This leads to an illegal map configuration.
To work around this issue and avoid the above error:
- Use an ECS-Verilog flow so that the fpga_dont_touch attribute is not used.
- Edit the VHDL (.vhf) files written by ECS and remove the fpga_dont_touch attributes on the CY4 primitives with unconnected CIN pins.