We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 13840

4.1i CORE Generator - Errors regarding "$recovery timing" occur on Block RAM COREGen components, even in READ_FIRST mode


Keywords: COREGen, recover, block RAM, blockRAM, BRAM, error, simulation, READ_FIRST, ModelSim

Urgency: Standard

General Description:
I am using the CORE Generator DP Block Memory behavioral model; for a block memory targeting a Virtex-II in READ_FIRST mode, a "$recovery" error occurs when an address is written to with one port and read simultaneously by the other.


This should not be a problem, as the Virtex-II architecture can cope with this functionality. It is safe to continue the simulation, even if this warning has been reported. (A change request has been scheduled to fix this problem.)

We recommend that you run a timing simulation to ensure that the correct, expected functionality is being achieved.
AR# 13840
日期 10/09/2003
状态 Archive
Type 综合文章