When using the "FreezeDCI" BitGen option as described in (Xilinx Answer 13012), I notice that my split-terminated I/Os are showing an unexpected DC offset.
This is an expected result of freezing the DCI clock. The DC offset may affect the following I/O standards:
DCI Drivers: HSTL_II_DCI, HSTL_IV_DCI, SSTL2_II_DCI, SSTL3_II_DCI, GTL
DCI Receivers: HSTL (All), SSTL (All), GTL, LVDS_DCI, LVDS_EXT_DCI
SSTL is the most affected, and it can have approximately +/- 100 mV of DC offset. However, with "FreezeDCI" the worst-case error is 5% worse than it was previously over all voltages and temperatures. This is still an excellent way to terminate signals; it often works better than a resistor because of the stubs and because the resistor termination is not on the die.
The DC offset is between banks. All I/Os in the same bank have the same DC offset. Consequently, when the I/Os of the same bus are kept in the same bank, the offset is avoided. The offset may be higher on I/O standards with higher VCCO. In some cases, you may see DC offsets higher than +/-100 mV with VCCO = 3.3V. Please see (Xilinx Answer 11814) for more information on DCI error tolerance.