AR# 13966


4.1i XST - "ERROR:Xst:850 - Unsupported exactly equal expression"


Keywords: While, loop, Verilog, XST, for, VHDL

Urgency: Standard

General Description:
When I use an exactly equal or unequal statement in Verilog, the following error is reported:

"ERROR:Xst:850 - "project_file.v", line xx: Unsupported exactly equal expression."


Exactly equal/unequal expressions are not yet supported. These are the operators "===" and "!==". They will be supported in a future XST release.

Meanwhile, one way to work around this issue is to use the standard equal/unequal expressions "==" and "!=".

This problem has been fixed with the release of the 5.1i software.
AR# 13966
日期 08/06/2003
状态 Archive
Type 综合文章
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