.prj names two source files, .vhd and .vhd, that both define the same primary unit, "">

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AR# 13975

XST - "ERROR:HDLParsers:3340 - Project file .prj names two source files, .vhd and .vhd, that both define the same primary unit, "

描述

General Description:

When I compile a VHDL design, XST reports the following error:

"ERROR:HDLParsers:3340 - Project file <project>.prj names two source files, <file1>.vhd and <file2>.vhd, that both define the same primary unit, <my_entity>"

解决方案

This error indicates that multiple instances of the named entity were found during HDL parsing. Port names are irrelevant; the name must be unique for each entity within your project.

To resolve this conflict, remove one of the instances from the project, or modify the name of one of the entities.

AR# 13975
日期 12/15/2012
状态 Active
Type 综合文章
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