AR# 14124


6.2 System Generator for DSP - Interleaver fails in MAP for Virtex-II Pro parts


I am using System Generator for DSP to create a design that contains an Interleaver core, and I am targeting a Virtex-II Pro part. When I run the implementation tools, MAP fails with an error similar to the following: 


"ERROR:Pack - No legal placement was found for the RPM 

"fc_rdy_74478_7/row1/fg1/fc1/main/dinsr1/row1". The RLOC values don't 

correspond to valid sites for the given device. The RLOC values are 

interpreted differently because of the presence of the RPM_GRID=GRID 

constraint found on FDE symbol "BU708" (output signal=N583). This RPM may 

include portions which are dependent on a specific device. Verify that the 

RLOC values are appropriate for this device."


This error is caused because RLOCs are going beyond the limits of the device. 


You can work around this issue by turning off RLOCs for the Interleaver core. To turn off the RLOCs, open the Interleaver/Deinterleaver Block parameters and deselect the "Use Placement Information for Core" check box. 



Please see (Xilinx Answer 30174) for a detailed list of LogiCORE Interleaver/De-Interleaver Release Notes and Known Issues.

AR# 14124
日期 05/14/2014
状态 Archive
Type 综合文章
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