AR# 14174


4.2i CORE Generator - Known Issues in the 4.2i IP Update #2 (E_IP2).


Keywords: E_IP2, 4.2i_ip_update#2, release note, COREGen, DA, FIR, filter, sine, cosine, lut, lookup, table, Virtex, adder, subtracter, FD, based, shift, register, accumulator, Virtex-II, block, RAM, memory, problem, single-port, dual-port, dual port, block memory, Asynchronous FIFO, release notes, distributor memory, FFT, 4.2i_ip_update_2, CORE Generator, IP Capture tool, HP, XST

Urgency: Standard

General Description:
This Answer Record contains the known issues that are addressed in 4.2i IP Update#2 (also referred to as "E_IP2").



Software Compatibility

The E_IP2 IP update is only compatible with Xilinx CORE Generator 4.2i, which is included with the ISE 4.2i software. This IP update should not be used with any other versions of CORE Generator (such as version 4.1i and 3.1i or earlier).

Service Pack Requirement

E_IP2 has been tested with Xilinx 4.2i Service Pack 1 . The latest service pack for 4.2i is available at:

Acrobat Reader Requirement

Acrobat Reader version 4 or later must be installed for core data sheets to be viewed. The latest Acrobat software may be downloaded from the following Adobe site:

If Acrobat Reader is not installed, you may not be able to open CORE Generator in Windows 98. For further information, please see (Xilinx Answer 12647).

Windows 2000

If you use a Windows 2000 platform, it is recommended that you use the "High Color" setting for your Display. For further information, please see (Xilinx Answer 12372).

HP Platform

1. When generating the following cores on an HP-UX or any HP platform, errors are reported, or CORE Generator hangs:

CAM v3_0,
8b/10b Encoder v3_0,
8b/10b Decoder v4_0

Please see (Xilinx Answer 14186).

2. CORE Generator hangs after generating following cores on an HP platform:

Reed-Solomon Encoder v3_0
Reed-Solomon Decoder v3_0
Interleaver/Deinterleaver v2_0
Viterbi v2_0

Please see (Xilinx Answer 14168).

Xilinx Implementation Software Issues

1. When a design is imported from 3.1i, "port mis-match " and "unconnected ports" messages appear during simulation and implementation.
Please see (Xilinx Answer 13062)

Updates Installer Tool

1. Update Installer cannot be used to install cores that have been captured by IP Capture Tool.
Please see (Xilinx Answer 14183)

2. The installer may take several hours, or the process seems to hang.
Please see (Xilinx Answer 12544).


1. DA FIR V7_0, DDC V1_0 GUI, and MAC FIR V1_0
In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format.
Please see (Xilinx Answer 14202).

2. MAC FIR V1_0
Incorrect results are given for 2-tap non-symmetric and 2- or 3-tap symmetric filters.
Please see (Xilinx Answer 14242).

3. MAC FIR V1_0
After an initial load of the COE, the (COE) file can not be reloaded.
Please see (Xilinx Answer 14323)

4. DDS V4_1
When the Xilinx Implementation tool is run with DDS v4.1, the following error is reported:
"ERROR:Place:1751 - Structured logic associated with an F7 configuration could not be placed."
Please see (Xilinx Answer 14122).

5. DDC V1_0, MAC V2_0, SID (Interleaver/Deinterleaver) V2_0
When a design is synthesized with the above cores, errors report that certain modules are not defined.
Please see (Xilinx Answer 14341)


1. When VHDL behavioral simulation models for Virtex-II Block Memories (blkmemv2dp_v2_0.vhd and blkmemv2sp_v2_0.vhd) are compiled, the VHDL "-93 Compliancy" switch must be used.
Please see (Xilinx Answer 9734).

2. When XilinxCoreLib files are compiled using Synopsys VSS or VCSi, simulators report a number of warnings and errors.
Please see (Xilinx Answer 12630).

3. When XilinxCoreLib files are compiled using Cadence NCVHDL, simulators report a number of warnings and errors.
Please see (Xilinx Answer 14185).

4. Pre-compiled XilinxCoreLib libraries for ModelSim Xilinx Edition II (MXE) are currently undergoing testing. Once testing has been completed, the pre-compiled libraries will be available at:
AR# 14174
日期 10/08/2003
状态 Archive
Type 综合文章
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