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AR# 14249

4.1i XST - "ERROR:Xst:1031 - <file>.v Line xxx. Module '<my_module>' not defined"


Keywords: XST, Verilog, 1031, module, defined

Urgency: Standard

General Description:
When compiling a Verilog source file, XST issues the following error:

"ERROR:Xst:1031 - <file>.v Line xxx. Module '<my_module>' not defined."



This error will occur if a module is instantiated without being defined.

If the module instantiation represents a lower-level Verilog module to be synthesized by XST, ensure that XST has access to the HDL source. This means adding the Verilog file to the ISE (or XST, if using a command line) project, or using the "Verilog Search Paths" option to locate the needed Verilog code.


If the module instantiation represents a black box (IP core, EDIF netlist, etc.), the module must be declared in the Verilog source. A module declaration includes the port list as well as the size and direction of all the ports. This tells XST how the black box fits into the design and allows XST to perform rule checking.

Sample declaration:

module my_module (clk, rst, q, din, dout);
input clk, rst;
inout q;
input [7:0] din;
output [7:0] dout;
AR# 14249
日期 08/06/2003
状态 Archive
Type 综合文章