General Description: When I compile a Verilog design with XST, the following error occurs:
"ERROR:Xst:1059 - <file>.v Line x. Duplicate declarations of object 'name' in module 'my_module'."
This error occurs because, according to the XST Verilog parser, the instance "name" is declared multiple times. XST does not allow redundant declarations.
Search your Verilog source above the line number mentioned for another declaration. (It may be in a file that is referenced by an `include statement.) Ensure that the instance "name" is not duplicated.