.v Line xx. 'name' has not been declared"">

UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 14254

XST - "ERROR:HDLCompilers:28 - .v Line xx. 'name' has not been declared"

描述

General Description:

When I compile a Verilog design with XST, the following error is reported:

"ERROR:Xst:926 - <file>.v Line xx. 'name' not declared."

Why?

解决方案

Before using an instance of a signal, array, parameter, etc., the instance must first be declared. The XST parser scans a Verilog file from beginning to end, so any usage must be preceded by the declaration of that instance.

AR# 14254
日期 12/15/2012
状态 Active
Type 综合文章
的页面