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AR# 1428

FPGA Configuration - CCLK does not toggle in master mode

Description

Upon power-up or after the program pin is toggled Low then High, configuration fails. Done stays Low. Init goes High and stays High. Cclk does not toggle.

解决方案

One possible cause is that the mode pins are not set correctly. To use the mode pins as I/O after configuration, use the pull-down resistors on the mode pins, and verify that they are in a logic Low during configuration. The suggested pull-down resistor value is 1k to 2.3k ohms. This offsets the internal pull-up of 15k - 150k ohms. If a weaker pull-down resistor is used, then the voltage at the pin can exceed the maximum low-voltage threshold and be interpreted as a logic High voltage.

It is okay to simply tie the mode pins to either Vcc or Gnd.

AR# 1428
创建日期 08/21/2007
Last Updated 12/15/2012
状态 Active
Type 综合文章